Senior IC Test Engineer/manager
Beijing
Duty:
Responsible for DFT and ATPG of most advanced and 40nm SOC, in charge of chip manufacture test and function/electric test, interface with test house and assembly house.
Requirement:
- Master degree in EE, CS; 2 or more years experience in IC test
- Good at advanced DFT design and analysis, including mbist, scan, boundary scan
- Experience with chip manufacture test, function test and electric test
- At least one experience with bring test chip to volume production
- Experience with high speed interface like DDR2/3, SATA1/2/3, PCI-E is preferred.
- Self-motivated, team player
- Fluent English in reading, speaking and writing.
Senior IC Layout Engineer/manager
Beijing
Duty:
Responsible for back-end implementation advanced 40nm SOC, including floorplan, CTS, APR and physical verification. Co-work with Front-end engineer to deliver reach power/area/timing sign-off criteria on schedule.
Requirement:
- Bachelor degree in EE, CS; 3 or more years experience in IC layout design
- Familiar with popular backend EDA tools, especially Synopsys ICC
- Good experience with floorplan and APR for more than 10 Million gates design
- Experience with complex SOC chip containing 10 or more clocks and high speed PHYs
- Experience with 65nm process is preferred.
- Skilled in linux shell and tcl scripts.
- Self-motivated, team player
|
工作地点：Beijing 
