IC Design Engineer
Duty:
Participate in logic design of high performance and low power SOCs, including Micro-architecture definition, IP study and integration, power/clock/reset design, module level verification, silicon bring-up, etc.
Requirement:
- Master degree in EE, CS; 2 or more years experience in IC design
- Good at verilog logic design, problem analysis and solving.
- Design experience with ARM based SOC and basic knowledge with AMBA bus.
- DDR, USB, SATA, GMAC, HDMI, PCIE, Graphic or Video experience preferred.
- Known well Linux/Unix platform and scripting languages (Shell/Tcl/Perl/Python)
- Self-motivated, team player
- Fluent English in reading, speaking and writing.
IC Front-End Flow Engineer
Duty:
IC front-end implementation including synthesis, STA, Formal; DFT scheme definition and implementation, support backend team to analyze timing and power issue to deliver qualified Tapeout, assist verification team on post timing simulation.
Requirement:
- Master degree in EE, CS; 2 or more years experience in IC design
- Familiar with popular EDA tools, including DC, PT, TetraMax, Formality, etc
- Good at constraints design, timing analysis, timing closure.
- Front-end implementation experience in 2 or more chips.
- Skilled in linux shell and tcl scripts.
- Self-motivated, team player
- Fluent English in reading, speaking and writing
IC Verification Engineer
Duty:
Responsible for IP study and module level simulation, Participate in chip level or subsystem level function simulation, post timing simulation and low power verification.
Requirement:
- Master degree in EE, CS; 2 or more years experience in IC verification
- Verification experience in 2 or more chips;
- Familiar with VCS, Verilog, SV/SC, Verdi; Good at problem trace, debug and solving.
- DDR, USB, SATA, GMAC, HDMI, PCIE, Graphic or Video experience preferred.
- Experience in low power verification preferred;
- Known well Linux/Unix platform and scripting languages (Tcl/Perl/Python)
- Self-motivated, team player
- Fluent English in reading and writing
IC Prototype Engineer
Duty:
Responsible for FPGA prototype verification of SOC on FPGA and HW accelerate platform, implement IP module or subsystem or whole chip in FPGA platform, work with hardware team to design development board; work with software team to develop software drivers
Requirement:
- Master degree in EE, CS; 3 or more years experience with FPGA
- Familiar with Xilinx or Altera FPGA
- FPGA prototype experience in at least 2 chips.
- Familiar with ARM processors and AMBA/OCP bus.
- Skilled in problem trace and debug with logic analyzer and oscilloscope
- Known well Linux shell and/or perl scripts.
- Self-motivated, team player
- Fluent English in reading and writing
IC ESL Verification Engineer
Duty:
Responsible for SOC architecture verification on ESL platform, bus matrix design and bus performance analysis; build evaluation environment with high level model, study IP and write bus model and behavior, analyze bus traffic and memory bandwidth
Requirement:
- Master degree in EE, CS; 2 or more years experience in IC design
- Familiar with ARM processors and AMBA/OCP bus protocol.
- Experience in VCS simulation with bus model is preferred.
- Experience with DDR/mDDR/DDR2/DDR3 is preferred.
- Known well Linux shell and/or tcl/perl scripts.
- Self-motivated, team player
- Fluent English in reading and writing
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工作地点：Beijing
