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This is an opportunity to be part of an innovative team that develops the state-of-the-art multi-core network processors implemented in nanometer process technologies.
We are seeking a bright, self-motivated individual who excels in physical design. The successful candidate will be experienced in all aspects of physical design including, floor-planning, power planning, placement, clock design, routing, and timing closure. The ability to automate and script is required.
The position will demand a high level of execution, coupled with creative problem solving skills.
RESPONSIBILITIES:
- Participate in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly, P&R and timing closure.
- Responsible for all aspects of block level physical design and implementation.
- Static timing analysis, power and noise analysis and back-end (DRC, LVS) verification
JOB REQUIREMENTS:
- BSEE, MSEE Preferred
- 7+ years directly related physical design clock expertise in state of the art ICs with emphasis on VLSI physical design and methodology on 90, 65, 45 or 28 nanometer process nodes.
- Must have a proven track record of delivering tape-out quality GDSII with silicon success.
- Very strong programming skills (TCL/Perl/Shell/Make Flow) and the ability to automate design work through scripting.
- Experience in designing Chip level integration.
- Familiarity with RTL to GDS-II flow and design automation tools.
- Excellent Communication and Presentation skills.
- IBM Technology Flow – Advantage.
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工作地点：Beijing
