ASIC RTL Design Engineer
Beijing
By 2020, there will be 50 billion connections to the internet, whereby anything that can benefit from an internet connection will be connected. We are already starting to see this today. But, it’s just the beginning. Over the last 3-4 years Company has invested billions of dollars to move from a #1 position in Wireless Infrastructure (where we have >50% market share) to take claim as the #1 in Converged Infrastructure…end-to-end. There are a whole host of challenges you face when creating a single, fully converged, infrastructure that handles everything. This is a rare opportunity to be a part of something big…that’s technically challenging, and innovative, as well as change the world by creating a networked society!
For the last 15 years we’ve built ASICs, in-house, for these products our multi-service edge routing products. We are working on brand new chip architecture for our future generation platform. The ASICs we are building are state-of-the-art multi-core network processors that will be far more complex than previous generation ASICs. The will have more computational power, higher interface throughput, Parallel execution threads, higher clock frequency, Brand new architecture
Job Overview:
l RTL designer responsible for implementation in any of the following key areas of our next generation processor:
l Traffic Manager
l Memory sub-system including cache
l Packet Classification (Layer 2 classification experience is big plus)
l Algorithmic Search Units
l Execution Units
l Will be responsible for developing brand new features from grounds up
l Work with Architects and Micro-architects to provide solutions for complex technical challenges
l Responsible for delivering RTL from the uArch definition
l Responsible for the timing closure loop up to physical design placement
l Require to work with SDK, system and software teams
l Responsible for providing complete documentation for the block
Candidate Profile:
l 3-10 years of proven logic design experience in the areas of traffic manager/memory sub-system/packet classification /algorithmic search units/execution units
l Any Processor (General Purpose/Network/Video) background is definite plus
l Outstanding design delivery track record
l VERY strong verilog /system verilog programming skills
l Team players with proven experience in cooperation amongst key stake-holders
l Experience in high performance design with clock cycle beyond 1Ghz
l Strong driver with a keen sense of ownership and result orientation
l Knowledge about the following general ASIC design tool
u Conformal
u Static timing analysis tool
u Synthesis tool
u Formal verification tool experience a plus |
工作地点：Beijing
