Senior Signal Integrity and Backplane Design Engineer
Beijing
Responsibilities:
l Responsible for 10G+ High Speed SI solutions for Next Generation telecommunications equipment in the IP router.
l Responsible for the backplane architecture design. Design and analysis of high speed serial links for Backplane and chip to chip interfaces. Optimize design performance and manufacturability
l Responsible for board level and system level signal integrity analyze, making design rule and constrains, review the PCB layout design.
l Responsible for 2D, 3D and channelize analyze simulation
l Responsible for high speed board and system signal integrate verification.
l Cooperate with FPGA, PCB and System engineers to analyze and solve the problem in products
Qualifications/Requirements:
l Must have significant, recent signal integrity, backplane and SerDes experience.
l Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE, Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and other tools.
l Experience of using oscilloscopes, TDRs, VNAs, BertScope to perform measurements to collect data for design validation and simulation correlations.
l Self-motivated with strong communication and teamwork skills.
l Good at English reading, writing and communication
l Experience in Core router, Edge router or similar product, in large telecomm company.
l MSEE or PhD with 5 years of experience in signal integrity area.
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工作地点：Beijing
