Beijing

 

·         Responsible for 10G+ High Speed SI solutions for Next Generation telecommunications equipment in the IP router, switch and transmission products.

·         Responsible for the backplane architecture design. Design and analysis of high speed serial links for Backplane and chip to chip interfaces.  Optimize design performance and manufacturability

·         Responsible for board level and system level design rule and constrains, review the PCB layout design.

·         Responsible for 2D, 3D and channelize analyze simulation

·         Responsible for high speed board and system signal integrate verification.

·         Cooperate with FPGA, PCB and System engineers to analyze and solve the problem in products

 

·         Must have significant, recent Backplane and SerDes experience.

·         Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE,Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, andother tools.

·         Experience of using oscilloscopes, TDRs, VNAs, BertScope to perform measurements to collect data for designvalidation and simulation correlations.

·         Self-motivated with strong communication and teamwork skills.

·         Experience in Core router, Edge router or similar product, in large telecomm company.

·         MSEE orPhD with 10years of experience.