BBA FPGA

 

Beijing

 

Responsibilities & Main Tasks

- To carry out the assigned tasks and report progress to the R&D Head and project manager.

- To support the R&D or HW manager in the task to ensure that the HW design activities fulfill the needs within the R&D Center in an efficient way.

- HDL logic design and verification

 

Qualifications

- Master degree in CS, EE, Telecom or equivalent

- Excellent knowledge of Communication systems and their design

- Minimum 5 years experience in HDL logic design and verification

- Minimum 4 years experience in a relevant technical areas; e.g. Transmission networks (SDH, EoS, Metro Ethernet MEF etc), Access technologies (xDSL, PON, CATV etc) or IP Access Aggregation (Ethernet Switching, Routing, QoS etc), with proven industry experience.

- Detailed architectural knowledge of Xilinx and Altera FPGA's

- Good communication skills and social ability.

- Teamwork

- Fluent English in reading and writing